Note: Instructions on Petalinux BSP creation (rather Petalinux flow from scratch) is provided in Appendix1 below. 2.3.1.1 Create PS EMIO Ethernet project from PetaLinux BSP Run petalinux-create command on the console petalinux-create -t project -s īash> petalinux-package -boot -fsbl zynq_fsbl.elf -fpga pl_eth_sfp.bit -u-boot (1000base-x)Ģ.4.1.8 SD Images SD Deployable binaries:- a) BOOT.bin b) image.ub Copy BOOT.BIN and image.ub from $PETALINUX/ xapp1082_pl_eth_1000x/images/linux to SD partition and run the setup. 2.3 PS-EMIO Ethernet 2.3.1 PS-EMIO BSP installation for 1000Base-XPS-EMIO Ethernet project provides installable BSP, which includes all necessary design sources and configuration files, including pre-built and tested hardware and software images, ready for download to your board or for booting in the QEMU system simulation environment. This wiki page assumes the user has already downloaded the XAPP package and extracted its contents to the XAPP home directory referred to as XAPP_HOME in this wiki. It also includes the binaries necessary to configure and boot the Zynq-7000 SoC board. Refer to section 3.4 for PetaLinux installation instructions.Ģ.2 Directory structure The XAPP1082 4.0 is released with the source code, Xilinx Vivado and Petalinux projects and an SD card image that enables the user to run the demonstration.Download Petalinux 2017.4 SDK software from Xilinx website download section.2.1 PetaLinux Installation Prerequisites This section lists the requirements for the PetaLinux Tools Installation $ vivado -source pl_eth_sgmii.tcl Rest of the steps remain same as covered in section XAPP v3.0. Navigate to hardware/vivado/scripts/pl_eth for PL Ethernet design.Open a Linux terminal or Vivado tcl shell in windows.Building PL Ethernet design in SGMII modeTo rebuild the hardware design, execute the following (after setting up Vivado environment). Navigate to hardware/vivado/scripts/ps_emio_eth for PS EMIO Ethernet design $ vivado -source ps_emio_eth_sgmii.tcl Rest of the steps remain same as covered in section XAPP v3.0. Open a Linux terminal or Vivado tcl shell in windows 2. Building PS-EMIO design in SGMII modeTo rebuild the hardware design, execute the following (after setting up Vivado environment). The steps for building designs "c" and "d" are mentioned below. The steps for building designs "a" and "b" mentioned above, are same as in "Vivado" section of XAPP v3.0. d) PL Ethernet implemented as soft logic in PL and connected to the SGMII physical interface in PL. c) PS Ethernet (GEM1) that is connected to a SGMII physical interface in PL through an EMIO interface. b) PL Ethernet implemented as soft logic in PL and connected to the 1000BASE-X physical interface in PL. a) PS Ethernet (GEM1) that is connected to a 1000BASE-X physical interface in PL through an EMIO interface. The designs support Vivado IP Integrator tool flow. Xilinx PHY driver supports for 1000Base-X and SGMIIįour designs are described in this application note.SGMII support to PS-EMIO and PL-Ethernet designs.The design details (block diagrams) are provided in XAPP1082 2. Understanding & Benchmarking Ethernet performance.Hardware and software design build steps.In addition, this document includes Ethernet performance measurements with and without checksum offload support enabled. The designs provided with this application note enable the use of multiple Ethernet ports, and provide kernel-mode Linux device drivers. This application note also describes the implementation of PL-based Ethernet supporting jumbo frames. This application note describes using the processing system (PS) based gigabit Ethernet MAC (GEM) through the extended multiplexed I/O (EMIO) interface with the 1000BASE-X physical interface using high-speed serial transceivers in programmable logic (PL). IntroductionThe focus of this application note is on Ethernet peripherals in the Zynq®-7000 SoC.
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |